Processor modeling using SMDL

SMDL is a simple yet powerful language for describing a processor. Using SMDL, processor information required by developer tools can be specified in a single unified model. SMDL allows the specification of a processor as a hierarchy of instruction bundles, instructions and operands.

CPU Designers can use an iterative approach, creating basic SMDL register model in about 1 hour and then iteratively add operands and instructions one by one, adding test cases and testing new instructions instantly using dtlt (line translator), dtas (CDK assembler) and simulator (CDK dtsim).

Note that SMDL allows instruction set architecture information for a processor to be specified in a hierarchical notation. An SMDL model can include operands, instructions and bundles in multiple representations Viz., mnemonics for assembly language, binary code for machine code and STC Icode for intermediate code representation. STC Intermediate code is a language for describing the semantics of the Instruction Set Architecture of a processor.

CDK Developer Tools are a revolution in the way tools are built for new processor designs - by processor architects or in house tools groups as the processor is designed rather than by third party tool vendors !

To schedule a discussion with our architect or sales engineer please email sales@sankhya.com