Dynamically Targetable Tools Framework TM
DTTF, which stands for Dynamically Targetable Tools Framework, allows for tools that need information about a processor architecture, to be able to load a processor model, described using SMDL (the SANKHYA Machine Description Language) at run-time, and dynamically target/support the processor described in the model.
A processor model for a simple RISC like processor can be developed in as little as 3 days and the STC tools can then just load the model file for supporting the processor described. Supporting more complex processors (VLIW, DSP) will take about 4-8 weeks.
This novel approach is especially useful when a processor is being designed or a reconfigurable processor is modified (in a minor way) by an end-user, because changes to the processor architecture only impact the processor model file, and the tools need no changes or rebuild, as they can load the model at execution time !
The wide spread availability of FPGA's has opened up the world of CPU design and brought it within the reach of educational institutions, research organizations and all other SoC/CPU designers. DTTF and STC make it possible to develop programs, assemble them, simulate them and debug them using a graphical debugger.